1. Field of the Invention
The present invention relates to junction field effect transistors, a semiconductor memory device containing the transistor and methods for manufacturing the transistor and the memory device. More particularly, the invention relates to junction field effect transistor structures conducive to further miniaturization, to semiconductor memory structures (such as dynamic random access memory structures) suitable for higher memory cell integration, and to methods for manufacturing the transistor and the memory device.
2. Description of the Prior Art
Recent years have seen a rapid growth in the demand for semiconductor memory devices spurred by the widespread use of data processing devices such as computers that use the memory devices. Functionally, the memory devices are required to deliver two things: greater storage capacity and higher speed of operation. Against this background, technologies of semiconductor memory devices are being developed for their greater integration, higher responsiveness and higher reliability.
Of today's semiconductor memory devices, the dynamic random access memory (DRAM) is capable of receiving and outputting data in a random manner. The DRAM is generally made of memory cell arrays and peripheral circuits. The memory cell arrays constitute a memory area for accumulating large quantities of input data. The periphery circuits designate memory cells that are unit memory circuits and control the output and input of data to and from the outside.
FIG. 33 is a block diagram of a typical prior art DRAM structure. In FIG. 33, the DRAM 50 comprises a memory cell array 51, a row and column address buffer 52, a row decoder 53, a column decoder 54, a sense refresh amplifier 55, a data-in buffer 56, a data-out buffer 57 and a clock generator 58. The memory cell array 51 accumulates data to be stored. The row and column address buffer 52 receives from the outside an address signal A0-A9 for selecting a memory cell that constitutes a unit memory circuit. The row decoder 53 designates a memory cell by decoding a row address signal. The column decoder 54 designates a memory cell by decoding a column address signal. The sense refresh amplifier 55 reads the signal from the designated memory cell by amplifying it. The data-in buffer 56 receives data signals from the outside, and the data-buffer 57 outputs stored data to the outside. The clock generator 58 generates and sends a clock signal to the relevant circuit components, the signal acting as their basic control signal.
The memory cell array 51, occupying a large area of the semiconductor chip, has a plurality of memory cells arranged in matrix fashion for storing data units. FIG. 34 is an equivalent circuit diagram of a prior art DRAM with four-bit memory cells constituting the memory cell array 51. In FIG. 34, the memory cell array 51 contains a plurality of word lines WL extended parallelly in the row direction and a pair of bit lines BLa and BLb arranged parallelly in the column direction. Near the points of intersection between the word lines WL and the bit lines BLa and BLb are memory cells M. Each memory cell M shown is made of a capacitor C for accumulating a data charge and a metal insulator semiconductor (MIS). That is, each memory cell is a one-transistor, one-capacitor memory cell. Because of their simple structure, memory cells of the above type are conducive to higher degrees of memory cell array integration and are thus used extensively in large-capacity DRAM's. FIG. 34 shows a loop bit line setup in which the two bit lines BLa and BLb are arranged in parallel with the sense amplifier.
The prior art DRAM works illustratively as follows: in FIG. 33, data are stored in the memory cell array 51 of N (n.times.m) bits. The memory cell address data by which to write or read data to or from the memory are held in the row and column address buffer 52. The row decoder 53 selects one of n word lines to connect electrically m-bit memory cells via bit lines to the sense refresh amplifier 55. The column decoder 54 selects one of m bit line pairs to connect one sense refresh amplifier 55 with the data-in buffer 56 or data-out buffer 57. In this manner, each desired memory cell is selected from the N-bit memory cell array 51 based on the address signal.
Referring to FIG. 34, the gate electrode of an MIS transistor Tr is connected to the word line WL. One of two source/drain electrodes is connected to one of two electrodes of a capacitor C; the other source/drain electrode is connected to the bit line BLa or BLb. In a data write operation, a desired word line WL is selected so that a predetermined voltage will be applied to the word line WL of which the address is designated. This causes the MIS transistor Tr to conduct and allows the charge of the bit line BLa or BLb to flow into the capacitor C where the charge is stored. In a data read operation, the predetermined voltage is applied to the selected word line WL. This causes the MIS transistor Tr to conduct and allows the charge in the capacitor C to be taken out via the bit line BLa or BLb.
Technologies of semiconductor memory devices are progressing rapidly toward higher integration. The trend is accompanied by a rush toward greater miniaturization of semiconductor device patterns that are formed in the memory devices. The standing demand for quicker, smaller semiconductor memory devices of larger capacities dictates that the memory devices have finer semiconductor device patterns inside. This applies in particular to the DRAM cells outlined above. It then becomes necessary not only to reduce the sizes of elements such as transistors and capacitor but also to reduce in size the memory cells made of such elements. The reductions contribute to decreasing the memory cell area which should occupy as little space as possible on the semiconductor substrate. Today, development of diverse memory cell structures is in progress in search of ever-smaller memory cell areas.
A typical memory cell structure of the 64-megabit DRAM is disclosed by M. Sakao et al. in IEEE IEDM Technical Digest, pp. 655-658, 1990, "A Capacitor-Over-Bit-Line (COB) Cell with a Hemispherical-Grain Storage Node for 64 Mb DRAMs." FIG. 35 is a cross-sectional view of the prior art DRAM cell structure disclosed in the above reference. In FIG. 35, two memory cells are formed on the main surface of a p-type silicon substrate 1. The memory cells are surrounded by isolation oxide films 10 and share a bit line contact 8. On the right- and left-hand sides of the bit line contact 8 are gate electrodes 5c of an n-channel MIS transistor. The n-channel MIS transistor comprises the gate electrodes 5c formed on the p-type silicon substrate 1 with a thin gate isolation film 17 interposed between substrate and electrode, and n-type source/drain impurity diffusion layers 18 disposed on the right- and left-hand sides of the gate electrodes 5c. One n-type source/drain impurity diffusion layer 18 is connected to bit lines 6 and the other n-type source/drain impurity diffusion layer 18 to storage nodes 7 that constitute capacitors. The gate electrodes 5c of the MIS transistor double as first word lines connected to the transistor. Because the memory device adopts the loop bit line structure, the isolation oxide films 10 are topped with the first word lines 5c connected to the gate electrodes of adjacent memory cells. The bit lines 6, connected to the bit line contact 8, are formed above the first word lines 5c. Above the bit lines 6 are second word lines 5b which, formed of an aluminum wiring layer, are connected in parallel with the first word lines 5c.
To raise the degree of integration from the 64-megabit DRAM of FIG. 35 to DRAM's of 256 megabits and further on to those of one gigabits requires reducing progressively the area of each memory cell on the semiconductor substrate. This is where difficulties are experienced. In particular, attempts to reduce in size the MIS transistors constituting memory cells often involve having hot carrier generated by impact ionization at the pinched-off portions of the drain region edges. Hot carrier generation leads to long-term degradation of transistor characteristics. With reliability thus compromised, the miniaturization of MIS transistor channel lengths in the submicron region turns out to be very difficult.
U.S. Pat. No. 4,423,490 discloses a DRAM using junction field effect transistors, a variation of the same field effect transistor type as the MIS transistor. However, the disclosure does not include transistor structures for enhancing the integration of junction field effect transistors.